1. Field of the Invention
The present invention relates to a signal processing device, and more specifically to a signal processing device for suppressing a noise in a signal outputted from a charge transfer device type solid state image sensor.
2. Description of Related Art
Referring to FIG. 1, there is shown a conventional charge transfer device type image sensor, typified particularly by a CCD (charge coupled device) type image sensor, generally designated by Reference Numeral 71.
As extremely simply depicted in FIG. 1, the CCD image sensor 71 is basically composed of a number of photosensor cells such as photodiodes 72 arranged in the form of a matrix having a plurality of rows and a plurality of columns, a plurality of vertical charge transfer devices 73 each located along a corresponding column of photodiodes so as to receive an electric charge from all the photodiodes of the corresponding column in parallel and to vertically transfer the received electric charges, a horizontal charge transfer device 79 located along an output end of all the vertical charge transfer devices so as to receive an electric charge from all the vertical charge transfer devices in parallel and to horizontally transfer the received electric charge, and an electric charge detection circuit 74 having an input coupled to an output end of the horizontal charge transfer device.
An analog signal outputted from the electric charge detection circuit 74 is caused to pass through a buffer 78, a clamp circuit 75, a sample-hold circuit 76, a low pass filter 77, and an amplifier 80 for various signal processings. An output of the amplifier 80 is connected to an output terminal "OUTPUT". Thereafter, in some cases, the analog signal outputted from the amplifier 80 is supplied an A/D converter (analog-to-digital converter) (not shown), so that a digital signal is obtained.
In various solid image sensors including the above mentioned conventional CCD solid state image sensor, a so called "reset noise" occurs when there is used a charge detection circuit such as a floating diffusion amplifier type (called a "FDA type" hereinafter) charge detection device or a ring junction gate type charge detector.
Now, for the purpose of explaining a mechanism of generation of the reset noise, the FDA type charge detection device will be explained with reference to FIG. 2, which is a partial diagrammatic sectional view of an output part of the CCD structure including a typical FDA type charge detection device, in combination with potential diagrams showing changes of potentials at various portions for illustrating a charge transfer process.
As shown in FIG. 2, the output part of the CCD structure includes an N-type silicon substrate 85, which has a P-well 86 formed at a principal surface thereof. An N-well 87 is further formed on a surface of the P-well 86. The N-well 87 is terminated by a reset drain 82 which is formed in an end portion of the P-well 86.
A gate oxide film (not shown) is formed to cover the principal surface of the semiconductor substrate 85. On the gate oxide film (not shown), a plurality of transfer electrodes and a final transfer gate electrode (both of which are provided for the CCD transfer structure but are not shown for simplification of the drawing), an output gate electrode 83, and a reset gate, electrode 81 are foraged in the named order toward to the reset drain 82, so that the reset gate electrode 81 is positioned adjacent to the reset drain 82.
A portion of the N-well 87 between the output gate electrode 83 and the reset gate electrode 81 constitutes an electrically floating diffusion region 84. Between this floating diffusion region and the P-well 86, a charge detection capacitor is formed. This floating diffusion region 84 is connected through an output line 84A to an input of a source follower 13. In addition, a reset transistor is foraged of the reset drain 82, the reset gate 81 and the floating diffusion region 84.
With the above mentioned arrangement, the reset drain 82 is biased to a fixed reset drain voltage, for example, a voltage supply voltage VDD, and the output gate 82 is biased to an appropriate fixed voltage VOG that does not become a hindrance in the charge transfer. In addition, a reset signal .phi.R is applied to the reset gate electrode 81. When the reset signal .phi.R is applied to the reset gate electrode 81, the charge detection capacitor (floating diffusion region) 84 is reset to the same potential as that of the reset drain voltage VDD connected to the reset drain 82.
After the charge detection capacitor 84 is reset, the charge detection capacitor is put in a floating condition. In this condition, a signal electric charge transferred from the CCD transfer structure is injected into the charge detection capacitor 84, so that a potential on the charge detection capacitor 84 changes, from the potential on the charge detection capacitor 84 just after the charge detection capacitor 84 is reset, in proportion to the amount of the signal electric charge accumulated in the charge detection capacitor 84. Here, in the case that the signal electric charge is electrons, the lower the potential on the charge detection capacitor 84 is than the after-reset potential which corresponds to a reference level of a black, the more the amount of the signal electric charge accumulated in the charge detection capacitor 84 is. Thus, this change in the potential on the charge detection capacitor 84 is detected as an output signal.
As shown in the potential diagram at the timing T1 in FIG. 2, the reset transistor is conductive (ON) at the timing T1. At this time, a voltage substantially equal to the voltage supply voltage VDD is obtained from the output line 84A.
As shown in the potential diagram at the timing T2 in FIG. 2, the reset transistor is brought from the ON condition into an OFF condition at the timing T2. At this time, the charge staying under the reset gate 81 is distributed into a region of the reset drain 82 and a region of the charge detection capacitor 84. The charge flowed into the region of the charge detection capacitor 84 causes to further drop the potential on the charge detection capacitor 84, to a potential lower than the reset drain voltage. Thus, the reset noise occurs.
This reset noise is determined by ambient temperature, the capacitance of the charge detection capacitor and the gate capacitance. The reset noise is also called a "partition noise", which is discussed in detail in N. TERANISHE et al., "Partition Noise in CCD Signal Detection", IDEM--INTERNATIONAL ELECTRON DEVICE MEETING, Dec. 1-4, 1985, pp 452-455, the disclosure of which is incorporated by reference in its entirety into the present application.
This reset noise is on the order of 500 mV, which is larger than a level of an output signal in a CCD image sensor internally containing a voltage amplifier. In addition, the amplitude of the reset noise is independent of the output signal itself, and therefore, if the reset noise is superposed on the output signal, a dynamic range of the signal processing circuit is restricted by the reset noise, so that it is difficult to obtain a satisfactory signal amplitude. In particular, this problem is remarkable, when a gain of the voltage amplifier is made large because the signal voltage is small.
In a conventional circuit as shown in FIG. 3 for cancelling the reset noise, a charge detection circuit 100 is added with a circuit 100A for generating a signal equivalent to the reset noise superposed on the signal detected in the charge detection circuit 100. The charge detection circuit 100 includes a transistor 11 corresponding to the reset transistor formed of the reset drain 82, the reset gate 81 and the floating diffusion region 84 shown in FIG. 2, and a capacitor 12 corresponding to the charge detection capacitor 84 between the floating diffusion region and the P-well 86 shown in FIG. 2. A gate of the transistor 11 is connected to receive a reset pulse .phi.R. Similarly, the reset noise equivalent signal generating circuit 100A includes a transistor 11A equivalent to the transistor 11 and a capacitor equivalent to the capacitor 12, and a gate of the transistor 11A is similarly connected to receive the reset pulse .phi.R.
An output of the charge detection circuit 100 is applied through a current amplifier 13 to a first input A1 of a differential amplifier 91, and similarly, an output of the reset noise equivalent signal generating circuit 100A is applied through a current amplifier 13A to a second input B1 of a differential amplifier 91. Thus, this differential amplifier 91 outputs a differential signal, in which the reset noise is cancelled.
The differential signal outputted from the differential amplifier 91 is outputted through a first inverting amplifier 14, a second inverting amplifier 15 associated with a clamp circuit 10, and a source follower output circuit 13B.
The above mentioned conventional circuit requires, in addition to the charge detection circuit 100, the reset noise equivalent signal generating circuit 100A for generating a signal equivalent to the reset noise superposed on the signal detected in the charge detection circuit 100. Therefore, an area occupied by the circuit is large, which is not suitable to a pattern design for a high density circuit. In addition, in order to ensure that the reset noise is efficiently suppressed by the differential amplifier, it is necessary that the reset noise equivalent signal generating circuit 100A is wired and located with a good balance. This is not suitable to microminiaturization.
Furthermore, since the differential amplifier itself is complicated, a circuit design is difficult.